With the coming of Ultra Large Scale Integrated (ULSI) DRAM devices, the sizes of memory cells have gotten smaller than micrometer such that the area available for a single memory cell has become very small. This causes reduction in capacitor area, resulting in the reduction of cell capacitance. Accordingly, for the memory cells in DRAM devices, the most important issue currently is how to promote the storage ability and operation stability of capacitors when the scales of devices still decreases and the integration increases. Thus, the susceptibility of capacitors due to at particle radiation and soft errors is lowered, and the increasing refresh frequency is improved.
For solving the issues above, the prior art approaches to overcome these problems have resulted in the development of the various types of capacitors, such as the trench capacitor and the stacked capacitor. However, The manufacture of the stacked capacitor causes difficulties due to the limitation of the lithography technique. Besides, enormous stacked structures for promoting storage capacity usually cause the crack of the stacked structure occurring due to the unequally stress. On the other hand, the storing capacity of trench capacitor can not be promoted effectively due to the scale of trench capacitor is restricted.
Refer to FIG. 1, the typical process for manufacturing a trench capacitor is shown, wherein a nitride layer 4 is formed on a substrate 2 firstly to be a stopper in latter steps. Then, a thick oxide layer 6 is formed on the nitride layer 4 to serve as an etching mask in latter etching step for forming the trench structure. Next, opens are formed on the oxide layer 6 and nitride layer 4 to expose the top surfaces of the substrate 2 and to define the pattern of the trenches. Subsequently, as illustrated in FIG. 2, an etching step is performed to etch the substrate 2 to form the trench structures 10 by using the oxide layer 6 as a mask. It is noted that much time is needed to etch the substrate 2 for forming the deep trench structures 10, and causes the oxide layer 6 suffering erosion in the etching step. Especially, the facets 12 usually occur on the sidewalls of the oxide layer 6, as shown in FIG. 2.
Refer to FIG. 3, after the trench structures 10 are formed, an etching back step is performed to etch the nitride layer 4 to pull-back the sidewalls 14 of the nitride layer 4. Thus, the conducting layer can be filled effectively into the trench structures 10 smoothly and completely. In general, the cycle time of etching the substrate 2 is elongated to form the deeper trench structures 10 for promoting the surfaces of the trench capacitors effectively. However, the oxide layer 6 as an etching mask always suffers severe damage. As illustrated in FIG. 4, the surface of the substrate 2 is exposed due to the nitride layer 4 suffered erosion after the oxide layer undergone the severe corrosion. It is noted that the contaminated particles, such as black silicon, occur on the surface of the substrate 2 when the nitride layer 4 is eroded. Accordingly, the yield of the trench capacitors produced in latter steps becomes lower and the dimensions of the trench structures become uncontrollable. In conventional technique, for solving the issues above, the cycle time to form the trench structures is lowered to prevent the nitride layer 4 from eroding. However, the depths of the capacitors are restricted due to the limited time, cause the reduction of the capacitor surfaces, and cause the descent of storage capacity. Further, even the cycle time of etching is limited, the nitride layer 4 on the periphery area of the wafer still eroded due to the loading effect. Namely, the nitride layer 4 above the periphery area of the wafer are eroded before the depths of the trench structures are etched to the predetermined values.